1. Field of the Invention
The invention relates to methods and systems for instruction execution and synchronization, and more particularly, to methods and systems for instruction execution and synchronization in a multi-thread processor.
2. Description of the Related Art
Recently, with the improvement in computer technologies and growth in processor designs, multi-thread processors which are processors with multiple threads have been widely used in many applications. The term “multi-thread” refers to a technique that allows multiple threads being executed in parallel, which may be implemented by software or hardware. Processing/computer systems with multi-thread may execute more than one thread at the same time, thus improving the overall processing performance of the system.
In general, parallel processing of multiple threads may be achieved by sequentially executing the instructions to separately control each of the threads or by indicating in the instructions to achieve the same goal for parallel processing of multiple threads. For the method of indicating in the instructions, it is required to configure a prediction register for each instruction (e.g. one bit data may be added into each instruction) and the compiler may then determine whether to skip an instruction according to whether the prediction register of the instruction is indicated as 1 or 0. By doing so, however, more complicated control logic units may be required and thus overhead of the compiler and the hardware complexity of the system may also be increased.